Method and apparatus for vector register with scalar values
US6530011B1 · kind B1 · utility
13Cited by
4References
63Claims
0Family size
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Key dates
| Filing date | Oct 20, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Oct 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar register and a second data in a vector register. Upon fetching the first data as a first operand and the second data as a second operand, the processing unit performs an operation between the first and second operands in response to an operator. After operations, the result is subsequently stored in a second scalar register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.