Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits
US6530014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1998 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Aug 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.