Radial arm memory bus for a high availability computer system
US6530033B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a memory configuration that is comprised of a memory controller, a single central switch, a data bus that is electrically coupled to the memory controller and the central switch, and a plurality of N memory modules, where each of the plurality of N memory modules is radially connected to the central switch by a corresponding memory module bus. The central switch is physically located on the motherboard and helps to provide in combination with the parallel connection of the memory modules, a point to point bus between the memory controller and the memory device on the memory module. The memory modules are field replaceable units and are electrically isolated from each other for use in high availability fault tolerant systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.