On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays
US6530049B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 6, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1428
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously. Prior to relocating the initial self-testing areas, the initial self-testing areas are rec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.