RTL annotation tool for layout induced netlist changes
US6530073B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Aug 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Register Transfer Language (RTL) annotation software tool that: (1) automatically calculates new RTL of a circuit to facilitate subsequent RTL level Engineering Change Orders (ECOs) on a circuit where gate level changes have occurred during layout; and (2) automatically calculates a gate level netlist that corresponds to the RTL ECO which can be fed to modern layout tools with minimal disruption to the existing layout. In a preferred embodiment, the tool is software driven, iterative, and tracks any changes that need to be made for any given circuit described by a hardware description language (HDL) though a series of intermediate and preliminary data files. The software receives input in the way of user input, constraints, and an RTL description for a pre-ECO circuit, and outputs the post-layout annotated RTL description. Subsequent ECOs are taken as input from the user in the form of a modified annotated RTL description and the software produces a corresponding gate level netlist for the ECO circuit, all the while preserving as much of the data generated during this process to avoid wasteful duplication of effort.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.