Method for manufacturing a semiconductor integrated circuit of triple well structure

US6531363B2 · kind B2 · utility

Assignee

• NEC CORPORATION · JP

Inventor

• Tetsuya Uchida · Nishio, JP

Key dates

• Filing date: Mar 5, 1999
• Grant date: Mar 11, 2003
• Expiry date: Mar 5, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not covered with the resist mask, and thereafter, forming a gate electrode and a source/drain diffused layer in a required well.