High voltage SOI semiconductor device
US6531738B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2000 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Aug 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/109
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×1012/cm2 so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.