Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof
US6531754B1 · kind B1 · utility
153Cited by
5References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Feb 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.