Method of placing die to minimize die-to-die routing complexity on a substrate
US6531782B1 · kind B1 · utility
11Cited by
34References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor package that may contain two or more dies. The method generally comprises the steps of (A) mounting a first die having a first side on an assembly apparatus and (B) mounting a second die having a second side and an adjoining third side on said assembly apparatus. The second die may be oriented such that (i) the second side and the third side both face the first side and (ii) the second side and the third side are both substantially nonparallel to the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.