Data processing system with improved latency and associated methods
US6531889B1 · kind B1 · utility
15Cited by
4References
58Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An configurable integrated-circuit device includes a plurality of regions that each contain electronic circuitry. The configurable integrated-circuit device also includes common circuitry adapted to provide at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.