Symmetric multiplexer
US6531910B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Sep 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6264
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer is provided that is symmetric in that substantially the same delay is experienced from any input of the multiplexer to the multiplexer output. It is realized that in conventional serial transmission systems, standard Current Mode Logic (CML) multiplexers are used which are asymmetric and exhibit different delays between select and data inputs. Because of these delays, conventional transmission systems experience jitter at high frequencies. To extend the operable range of communication systems, a symmetric multiplexer may be used which has substantially the same delay from any input to the multiplexed output, thus reducing jitter. For example, the multiplexer may be part of a communication system having a serial data transmission circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.