Volume rendering pipeline
US6532017B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1999 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of identical rendering pipelines are connected in parallel to read an array of voxels and to write an array of pixels. Each pipeline processes one voxel in one processing cycle of the pipelines. Each pipeline includes a plurality of serially connected different stages. The stages can include interpolation, classification, gradient estimation, illumination, and compositing stages. Interfaces connect identical stages in adjacent pipelines as one-way rings to communicate information associated with spatially adjacent voxels, and delay buffers connected parallel to particular stages communicate information associated with temporally adjacent voxels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.