Distribution of bank accesses in a multiple bank DRAM used as a data buffer
US6532185B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Mar 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9031
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.