Post-manufacture signal delay adjustment to solve noise-induced delay variations
US6532574B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic. Once the final signal adjustment configuration is determined, that configuration may be stored as a vector within a memory in the integrated circuit and read during power-up into a scan chain controlling the individual delay circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.