In-place method for inserting repeater buffers in an integrated circuit
US6532580B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for inserting in-place interconnect repeaters along the paths of interconnects of an integrated circuit is presented. The integrated circuit includes an interconnect layer on which an interconnect is routed, a silicon layer in which repeaters are implemented, and zero or more intervening layers. In accordance with the invention, reserved metal areas are defined on each intervening layer that resides between the interconnect layer and the repeater layer. Each interconnect net that requires a repeater for performance reasons is assigned to a repeater location. A repeater buffer is inserted at the assigned repeater locations. The interconnect net is cut into first and second subnets, which are then respectively connected through the reserved metal areas of the intervening layers to the respective input and output port of the repeater buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.