Method of fabricating TDMOS device using self-align technique
US6534365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Nov 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.