Encapsulation package and method of packaging an electronic circuit module
US6534711B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package (104) for encapsulating electronic components (102, 122, 550, 660) has at least two chambers (112, 212). Electronic components and modules within the chambers are interconnected by a leadframe (130) extending between the two chambers. One chamber may surround (FIGS. 1A, 2A) the other chamber, or it may be adjacent the other chamber (FIGS. 4, 4A, 8A, 9A). The sidewall (310) of one chamber (314) may be higher than the sidewall (308) of the other chamber (312). Each of the chambers may individually be filled with encapsulating material (713, 715). Temporary connections (742) to the leadframe may be made after one chamber is filled with encapsulating material, in an unfilled other chamber of the package which is subsequently filled with encapsulating material. A portion of a leadframe may extend to the exterior of the package. Openings (656, 658) may be provided in an external surface of the package for making connections with external components (650). The electronic components may include an RF-transponder and a pressure sensor, and the package may be mounted within a pneumatic tire (1012).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.