SRAM cell design

US6534805B1 · kind B1 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventor

• Bo Jin · Campbell, US

Key dates

• Filing date: Apr 9, 2001
• Grant date: Mar 18, 2003
• Expiry date: Apr 9, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

An embodiment of a memory cell includes a series of four substantially oblong parallel active regions, arranged side-by-side such that the inner active regions of the series include source/drain regions for p-channel transistors, and the outer active regions include source/drain regions for n-channel transistors. Another embodiment of the memory cell includes six transistors having gates substantially parallel to one another, where three of the gates are arranged along a first axis and the other three gates are arranged along a second axis parallel to the first axis. In another embodiment, the memory cell may include substantially oblong active regions arranged substantially in parallel with one another, with substantially oblong local interconnects arranged above and substantially perpendicular to the active regions. A method for fabricating a memory cell may include forming substantially oblong active regions within a semiconductor substrate, and forming substantially oblong local interconnects above and perpendicular to the active regions.