Hardmask designs for dry etching FeRAM capacitor stacks
US6534809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Mar 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.