DRAM cell with high integration density

US6534811B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Thomas Skotnicki · Meylan, FR
• Stephane Monfray · Eybens, FR
• Catherine Mallardeau · Grenoble, FR

Key dates

• Filing date: Jan 9, 2002
• Grant date: Mar 18, 2003
• Expiry date: Jan 9, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/373

Abstract

A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.