Stacked-gate flash memory device
US6534818B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.