Method and circuit for providing copy protection in an application-specific integrated circuit
US6535016B2 · kind B2 · utility
20Cited by
18References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | May 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2137
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.