Output buffer with compensated slew rate and delay control
US6535020B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant current circuit draws a current from the gate of the drive transistor to the second potential that is substantially independent of process and temperature variations, and therefore turns on the drive transistor at a constant rate, regardless of process and temperature variations. The compensation circuit draws a small current from the gate of the drive transistor to the first potential that is dependent upon process and temperature variations of the drive transistor, and therefore reduces the discharge rate of the gate of the drive transistor according to process and temperature variations of the drive transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.