Data bus fault detection circuit and method
US6535028B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Nov 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit is connected to a differential serial bus having first and second signal conductors. The receiver circuit includes a fault detection circuit which generates a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductors. A comparing circuit includes a plurality of comparators for comparing the difference signal, the first signal and the second signal to predetermined voltage levels. The comparing circuit also includes a plurality of logic units coupled to outputs of the comparators. A signal select circuit has a pair of inputs coupled to the first and second conductors, logic inputs coupled to logic outputs of the comparing circuit, and a signal output. The signal select circuit and the comparing circuit cooperate to control communication of the first and second conductors with the signal output as a function of fault conditions on the first and second conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.