Fully differential continuous-time current-mode high speed CMOS comparator
US6535029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | May 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/249
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed. By maintaining the comparator output at a substantially predetermined voltage level during non-operating periods, the switching characteristics of the comparator are enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.