Conditional clock buffer circuit
US6535036B1 · kind B1 · utility
13Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2002 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | May 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.