Injection locked frequency multiplier
US6535037B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Feb 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B19/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplication circuit is disclosed. The circuit includes a ring oscillator formed of an even number of phase shifting stages. Each phase shifting stage provides a high frequency output comprised of harmonics of the oscillation frequency of the oscillator. An input signal having a first frequency is injected into a feedback node of the oscillator, thereby injection locking the oscillator to the input signal such that the oscillation frequency of the oscillator is equal to the first frequency. An output signal is extracted from two of the phase shifting stages. One of the harmonic frequencies may be isolated in the output signal, thereby providing a clean output at a multiple of the input frequency. When the circuit is operated at high frequencies, the output signal consists substantially of the second harmonic frequency and the circuit operates as a frequency doubler. A pair of frequency doublers may be cascaded to form a frequency quadrupler capable of providing an output signal with a frequency greater than 10 GHz.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.