Three-level inverter controller reducing commutation loop inductance
US6535406B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/5395
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a gate control device for four self-arc extinction elements connected in series and two self-arc extinction elements connected in reverse parallel between the respective terminals of clamp diodes, individually, there is provided a PWM circuit that generates conduction control commands, and a gate control circuit including a delay circuit group that generates gate signals with respect to the respective self-arc extinction elements on the basis of respective conduction control commands. A pair of the self-arc extinction elements are rendered conductive at the same time, and another pair of the self-arc extinction elements are rendered conductive at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.