Semiconductor memory device capable of switching output data width
US6535412B1 · kind B1 · utility
8Cited by
5References
8Claims
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Key dates
| Filing date | Apr 24, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Apr 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.