Reading circuit for a memory cell
US6535429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Dec 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.