Method and apparatus for data sharing between two different blocks in an integrated circuit
US6535519B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1998 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Aug 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that includes an improved architecture that reduces the interface between different blocks by minimizing the wire connections between the two blocks. Specifically, the two blocks are structured to transfer data between the two blocks using only the data bus and a common clock, thus eliminating the need for an address bus. Each block contains data registers used for storing data. The data registers in one block correspond to the registers in the second block, with each block being aware of the memory structure of the other block. When one block needs data from the data registers of the other block, it requests the data and the sending block places the contents of its data registers on the bus sequentially. The requesting block reads the data from the data bus at the appropriate time by counting the number of clock cycles from the time that the data was requested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.