Method for reducing processor interrupt load
US6535942B1 · kind B1 · utility
5Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Feb 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing interrupt load in a multi-processor system is disclosed, whereby two central processors executing a real-time operating system can communicate with each other using a shared memory. A start pointer and end pointer are implemented preferably in logic. By detecting a difference in the logic values for the two pointers, the receiving CPU will receive interrupts only when new data from the sending CPU has arrived in the shared memory and the shared memory was empty. Consequently, the operating system will not be disturbed with unnecessary interruptions, and the interrupt load will thus be low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.