Memory embedded semiconductor integrated circuit and a method for designing the same

US6536013B2 · kind B2 · utility

Assignee

• SONY GROUP CORPORATION · JP

Inventors

• Toshio Kobayashi · Hino, JP
• Naoshi Ikeda · Yokohama, JP

Key dates

• Filing date: Dec 7, 2000
• Grant date: Mar 18, 2003
• Expiry date: Mar 15, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/00

Abstract

The present invention clarifies the conditions for the required element techniques to be technically superior and makes it easy to establish the development guideline during the development of a memory embedded semiconductor integrated circuit. The total resource CW of a fabrication technique is defined by utilizing the process number or mask number, etc., required for the fabrication; and the unit resource CWU is deduced by dividing the total resource CW with the effective wafer area; and the unit resource CWU multiplied by the area of the logic gate forming region is defined as the first effective technique resource CWL; that multiplied by the area of the memory cell forming region is defined as the second effective technique resource CWAM, that multiplied by the area of other regions is defined as the third effective technique resource CWP&IO; a plurality of techniques concerning the fabrication and/or design are compared by using the first to the third effective technique resources obtained as the above techniques are applied to, and from these techniques, those suitable to the required scales of the memory and the logic circuit are selected.