Standard block architecture for integrated circuit design
US6536028B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties. In this design style, the STANDARD BLOCKs are provided as general physical abstractions such that each STANDARD BLOCK is akin to a black box model with the majority of its internal design aspects invisible to the top-level assembly tool while selected design aspects remain visible. The global design aspects of each STANDARD BLOCK include its fun…
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