Devices and methods with programmable logic and digital signal processing regions
US6538470B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.