Digital interface with low power consumption
US6538474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jul 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention proposes an interface circuit having a very low power consumption and generating very low interference noise in the sensitive band of ratio chips. It is advantageously used to interface a microprocessor with a baseband radio processor in a telecommunication device, for example in DECT or GSM phones. The interface of the invention is current-driven. It comprises a current driver for transmitting a current in a transmission line depending on the data to be transferred. It also comprises a current receiver. The current receiver has an input node and an output node interconnected via a current mirror circuit, so that the voltage on said input node is near to the ground voltage and the voltage on said output node is changing depending on the transferred data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.