Method and circuits for compensating the effect of switch resistance on settling time of high speed switched capacitor circuits
US6538491B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched capacitor circuit includes an operational transconductance amplifier, a feedback stage having a first switched capacitor and a first time constant, and a load stage having a second switched capacitor and a second time constant. The first time constant and the second time constant are equal to each other to improve settling of the circuit. The first and second switched capacitors are coupled to an output of the operational transconductance amplifier via transistors. The transistors are sized so that the time constants of the feedback and load section are equal. In a further embodiment, the time constant of the feedback section is made greater than the load section, to further improve settling. On-state resistance of the transistors are controlled with respect to transconductance of the operational transconductance amplifier to maintain smaller error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.