On-chip power supply boost for voltage droop reduction
US6538497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J1/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for maintaining a stable power supply voltage. The method comprises using a power supply to provide power at a power supply voltage to a plurality of semiconductor devices. The power supply voltage is nominally at an optimal power supply voltage. A fast increase in the current can cause a drop in the supply voltage, since the high rate of change in current is through the package inductance. The power supply voltage is monitored. Further, a supplemental higher voltage power supply is used to boost the power supply voltage to substantially the optimal power supply voltage if the power supply voltage decreases by a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.