Phase-locked loop circuit
US6538519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase comparison circuit through a split loop filter. The oscillator has two varactors in parallel in its tuning circuit. The first branch of the loop filter includes an integrator filter generating a first error voltage and the second branch includes a low pass filter generating a second error voltage. The first error voltage controls one varactor and the second error voltage controls the other varactor. As a result the error voltages are effectively summed in the capacitance domain to obviate the need for a dedicated error voltage adder and to allow the total capacitance required in the loop filter to be reduced while still retaining an adequate signal to noise ratio in the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.