Methods and apparatus for producing a reference frequency signal with use of a reference frequency quadrupler having frequency selection controls
US6538520B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.