On-chip fixed-pattern noise calibration for CMOS image sensors
US6538695B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1998 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Nov 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/76
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An on-chip FPN calibration method and circuits scheme applying a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.