Image processor
US6538771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1998 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jan 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4105
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an image processor, multi-level image data are divided into blocks, and compressed in the unit of block. The compressed multi-level image data of a block are converted to compressed bi-level image data without expanding the multi-level image data. For example, the compressed multi-level image data on an image of uniform density are converted to compressed bi-level image data expressed with area gradation. In another image processor, the compressed multi-level image data of a block are converted to compressed multi-level image data, without expanding the multi-level image data. For example, the compressed multi-level image data on an image of bi-level image expressed with area gradation are converted to compressed multi-level image data of a half-tone image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.