Electrostatic discharge protective circuit
US6538868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B. There is a second resistor between the second node B and the system power source, and there is a capacitor between the second node B and the grounded node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.