Delay minimization for circuit emulation over packet switched (ATM) networks
US6538995B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1998 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Dec 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method of minimizing throughput delay in constant-bit-rate services carried over packet-based networks subject to variable delays, comprises, in one embodiment, the steps of receiving incoming packets in a buffer, reading out bits from the buffer at a clock frequency fi, continually monitoring the buffer fill level Li, determining the maximum fill level Lmaxj over a plurality of successive samples, determining the minimum fill level Lmink over a plurality of successive samples, adjusting the clock frequency fi to cause the maximum fill level Lmaxj to tend toward a target value TargetLmax, and adaptively changing said target value TargetLmax so that the minimum fill level Lmink tends toward a predetermined set-point. The rate of change of the target value TargetLmax is significantly slower than the rate of adjustment of clock frequency. The invention can be applied to other types of clock recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.