Method for the electric dynamic simulation of VLSI circuits
US6539346B1 · kind B1 · utility
1Cited by
8References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 6, 1999 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Aug 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.