Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system
US6539444B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.