Priority first come first serve interrupt controller
US6539448B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | May 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis. A priority encoder unit is included for receiving the interrupt requests stored in the storage units and providing the interrupt requests as outputs for processing by the microprocessor, on a priority basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.