Rotator circular buffer with entries to store divided bundles of instructions from each cache line for optimized instruction supply
US6539469B1 · kind B1 · utility
1Cited by
3References
19Claims
0Family size
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Inventor
Key dates
| Filing date | Oct 12, 1999 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises an instruction cache that stores a cache line of instructions and an execution engine for executing the instructions, along with a buffer to store a plurality of entries. A first logic circuit divides the cache line into instruction bundles, each of which gets written into an entry of the buffer. A second logic circuit reads out a number of consecutive instruction bundles from the buffer for dispersal to the execution engine to optimize speculative fetching and maximizing instruction supply to the execution resources of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.