System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain
US6539488B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits are disclosed which implement multiple channel media access control devices for controlling network communications. The integrated circuits include multiple channel slices which output data for transmission through the network. Each of the channel data are input to a single data memory, which reduces the size of the integrated circuit. Since only one data memory is used to buffer data from multiple channels, the data are first retimed from individual media access control circuit clock domains to a common host clock domain and then scheduled for output to the host. By retiming the data, integrated circuit signal throughput is enhanced. Deeply embedded transmit and receive FIFOs are provided to receive the channel data and implement shared memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.