Clock skew insensitive scan chain reordering
US6539509B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 1996 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for eliminating scan hold time failures of a scan chain. The method uses information resulting from the distribution of a clock throughout an integrated circuit. In particular, a scan chain is reordered according to the results of the distribution of the clock signal. The distribution of the clock signal provides groups of sequential circuit elements that form the scan chain. The method also includes reordering the sequential circuit elements within at least one group according to a clock skew of the clock signal within the at least one group. The method further includes ordering the groups according to a clock skew of the clock signal between the groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.